Quartus simulation


Can I have some help on Quartus implémentation projects please?

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I have learned to use Quartus software, and I think there must be a lot of people here who know how to use it.

I am not familiar with Quartus software. There are so many videos related to Quartus on youtube.

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I have been leraning it too as a student. I get some issue about thé waveform output from equations of “Universal shift register” and " 4 bits counter"

As a matter of fact, both of them have 4 mux from their combinatory part and in order to simulate, it takes to entry some inputs from their “truth table” as a rule. I did it but unfortunetely I do not have any response from the output while trying to simulate.


Hello, @Nysse

When you’re using the Quartus waveform simulator in order to view some internal signals (or ports isn’t being showed in waveform simulator). You must to add an specific compiler directive to say quartus sofware that you want to view this signal (i.e.: a wire) in a waveform, as follows in VHDL:

In the declarative part of an architecture declare boolean attribute. Then mark the desired signals with the attribute:

attribute keep: boolean;
attribute keep of Q: signal is true;

If you are using verilog insert a keep directive following the desired element:

wire Qa, Qb **/* synthesis keep */**;

You can see some examples of the above in this repository (VHDL only) of mine:

I hope it helps you. But if don’t you could post some captures of the problem and some code.

Furthermore I personally recommend to everyone using Quartus to move quickly to Modelsim in order to simulate their designs because of its features, flexibility and be widespread in the electronic design industry. A Modelsim version comes with Quartus and you can find some basic tutorials at intel university program:


Fun for everyone!! :wink:


Thank you @nicruireq for this sharing, it is an interesting sharing.